Datasheet

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
DRAM Controller
11-60 MCF5206e USER’S MANUAL MOTOROLA
For each transfer mask bit:
0 = Do not mask this type of transfer for the DRAM bank. A transfer of this type can
access the DRAM bank.
1 = Mask this type of transfer for the DRAM bank. A transfer of this type cannot
access the DRAM bank.
NOTE
The SC, SD, UC, and UD bits are ignored during external
master transfers. Therefore, an external master transfer can
access the DRAM banks regardless of the transfer masks.
NOTE
In determining whether an external master transfer address
hits in a DRAM bank, the portion of the address bus that is
unavailable externally is regarded as $0. That is, the external
master transfer address always has A[31:28] as $0 and those
bits of A[27:24] that are not programmed to be external
address bits as $0. In order for a bank to be accessible to an
external master, the address bits that are unavailable to the
external master must either be set to 0 in the DCAR or be
masked in the DCMR.
11.4.2.5 DRAM CONTROLLER CONTROL REGISTER (DCCR0 - DCCR1). Each
DCCR specifies the port size, page size, page mode, and activation of each of the DRAM
banks. Each DCCR is an 8-bit read/write control register. Master reset and normal reset
set all bits to zero.
PS - Port Size
This field specifies the data width of the DRAM bank. PS determines the byte lanes that
data will be driven on during write cycles and the byte lanes that data is sampled from
during read cycles.
00 = 32-bit port size - Data sampled and driven on D[31:0]
01 = 8-bit port size - Data sampled and driven on D[31:24] only
10 = 16-bit port size - Data sampled and driven on D[31:16] only
11 = 16-bit port size - Data sampled and driven on D[31:16] only
PS1 PS0 BPS1 BPS0 PM1 PM0 WR RD
76543210
00000000
NORMAL OR MASTER RESET:
DRAM Controller Control Register(DCCR)
Address MBAR + $57 (Bank0)
Address MBAR + $63 (Bank1)
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...