Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-61
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BPS - Bank Page Size
This field defines the bank page size for each DRAM bank for fast page mode and burst
page mode.
00 = 512 Byte page size
01 = 1 KByte page size
10 = 2 KByte page size
11 = Reserved
PM - Page Mode Select
This field selects the type of DRAM transfers generated for each DRAM bank: normal
mode, fast page mode, or burst-page-mode transfers.
00 = Normal Mode
01 = Burst Page Mode
10 = Reserved
11 = Fast Page Mode
WR - Write Enable
This field controls whether the DRAM bank can be accessed during write transfers.
0 = Do not activate DRAM control signals on write transfers
1 = Activate DRAM control signals on write transfers
RD - Read Enable
This field controls whether the DRAM bank can be accessed during read transfers.
0 = Do not activate DRAM control signals on read transfers
1 = Activate DRAM control signals on read transfers
11.5 DRAM INITIALIZATION EXAMPLE
The following sample assembly program illustrates a DRAM initialization procedure.
DRAM bank 0 is configured for a 4 MByte DRAM starting at address $00100000. The
DRAM port size is programmed to 32-bits (1 MByte x 32), the page size to 512 Bytes, and
fast page mode is enabled.
The Module Base Address Register (MBAR) is first written with the MODULE_BASE
value. This locates all the MCF5206e internal modules at address $00004000. Then the
DRAM Controller Timing Register (DCTR) is initialized to give the fastest possible DRAM
transfer waveform timing. The DRAM Controller Refresh Register (DCRR) is then written
causing DRAM refresh cycles to be generated once every 512 clocks (12.8 µsec for a 40
MHz system clock/9.5 µsec for a 54 MHz system clock). Once the DCRR is written, a
refresh cycle is immediately generated and refresh cycles are generated at the newly
programmed rate. Next, DRAM Controller Address Register 0 (DCAR0) is written, making
the starting address of DRAM bank 0 $00100000. DRAM Controller Mask Register 0
(DCMR0) is then written such that transfer address bits 18 - 16 are masked, making the
DRAM bank 0 address space 1 MByte. Therefore, DRAM bank 0 address space ranges
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