Datasheet

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
DRAM Controller
11-62 MCF5206e USER’S MANUAL MOTOROLA
from $00100000 - $001EFFFF. DRAM Controller Control Register 0 (DCCR0) is then
written making DRAM bank 0 have a 32-bit port size, a 512 Byte bank page size, generate
fast-page-mode transfers, and be enabled for both read transfers and write transfers. At
this point, DRAM bank 0 is initialized; however, DRAM read and write transfers will not be
generated until the global chip select is disabled by writing CSMR0.
#
# set up variables
#
MODULE_BASE equ 0x00004001# base address of internal module registers
DRAM0_BASE equ 0x0010# base address for Bank 0 DRAM
DCRRequ 0x46# DRAMC Refresh Register
DCTRequ 0x4a# DRAMC Timing Register
DCAR0equ 0x4c# DRAMC Address Register 0
DCMR0equ 0x50# DRAMC Mask Register 0
DCCR0equ 0x57# DRAMC Control Register 0
CSMR0equ 0x68# chip select Mask Register 0
#
# DRAMC initialization
#
move.l #MODULE_BASE, d0 # initialize MBAR
movec d0, mbar
move.l #MODULE_BASE, a0 # a0 points to the module base address
move.w #0x00, d0 # initialize for fastest DRAM cycle timing
move.w d0, (DCTR, a0) # (RCD=RSH1=RSH0=RP1=RP0=CAS=CP=CSR=0)
move.w #0x20, d0 # refresh every 512 clocks (15.4 uS @ 33 Mhz)
move.w d0, (DCRR, a0)
move.w #DRAM0_BASE, d0 # set DRAM0 start address at 0x00100000
move.w d0, (DCAR0, a0)
move.l #0x000e0000, d0 # mask low order bits for 1Mbyte address space
move.l d0, (DCMR0, a0) # DRAM0 address space is 0x0010-0x001effff
move.b #0x0f, d0 # 32-bit port, 512-byte page, fast page mode,
move.b d0, (DCCR0, a0) # readable/writable
# The global chip select activates for ALL external transfers after reset until
# it is disabled. Therefore, before a DRAM transfer can be done, the global chip
# select must be disabled by writing CSMR0.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...