Datasheet

UART Modules
MOTOROLA MCF5206e USER’S MANUAL 12-3
The receiver accepts serial data on the channel receiver serial data input (RxD); converts
it to parallel format; checks for a start bit, stop bit, parity (if any), or any error condition;
and transfers the assembled character onto the bus during read operations. The receiver
can be polled or interrupt driven. Refer to Section 12.3.2.2 Receiver for additional
information.
12.1.2 Baud-Rate Generator/Timer
The 16-bit timer, clocked by the system clock, can function as an asynchronous x16 clock.
In addition, you can tie an external clock to one of the TIN pins of a MCF5206e timer for
use as a synchronous or asynchronous clocking source for the UART. The baud-rate
timer is part of each UART and not related to the ColdFire timer modules.
12.1.3 Interrupt Control Logic
An internal interrupt request signal (IRQ) notifies the MCF5206e interrupt controller of an
interrupt condition. The output is the logical NOR of all (as many as four) unmasked
interrupt status bits in the UART Interrupt Status Register (UISR). You program the UART
Interrupt Mask Register (UIMR) to determine which interrupts will be valid in the UISR.
You program the UART module interrupt level in the MCF5206e interrupt controller
external to the UART module. You can configure the UART to supply the vector from the
UART Interrupt Vector Register (UIVR) or program the SIM to provide an autovector when
a UART interrupt is acknowledged.
You can also program the interrupt level, priority within the level, and autovectoring
capability in the SIM register ICR_U1.
12.2 UART MODULE SIGNAL DEFINITIONS
The following paragraphs contain a brief description of the UART module signals. Figure
12-2 shows both the external and internal signal groups.
NOTE
The terms assertion and negation are used throughout this
section to avoid confusion when dealing with a mixture of
active-low and active-high signals. The term assert or
assertion indicates that a signal is active or true, independent
of the level represented by a high or low voltage. The term
negate or negation indicates that a signal is inactive or false.
12.2.1 Transmitter Serial Data Output (TxD)
This signal is the transmitter serial data output. The output is held high ('‘mark’' condition)
when the transmitter is disabled, idle, or operating in the local loopback mode. Data is
shifted out on this signal on the falling edge of the clock source, with the least significant
bit transmitted first. All UART pins are muxed with the parallel port. On UART 2, RTS is
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...