Datasheet

UART Modules
12-6 MCF5206e USER’S MANUAL MOTOROLA
12.3.2 Transmitter and Receiver Operating Modes
The functional block diagram of the transmitter and receiver, including command and
operating registers, is shown in Figure 12-4. The following paragraphs describe these
functions in reference to this diagram. For detailed register information, refer to subsection
12.4 Register Description and Programming.
12.3.2.1 TRANSMITTER. The transmitter is enabled through the UART command
register (UCR) located within the UART module. The UART module signals the CPU
when it is ready to accept a character by setting the transmitter-ready bit (TxRDY) in the
UART status register (USR). Functional timing information for the transmitter is shown in
Figure 12-5.
The transmitter converts parallel data from the CPU to a serial bit stream on TxD. It
automatically sends a start bit followed by
• The programmed number of data bits
• An optional parity bit
• The programmed number of stop bits
The least significant bit is sent first. Data is shifted from the transmitter output on the falling
edge of the clock source.
After the transmission of the stop bits, if a new character is not available in the transmitter
holding register, the TxD output remains in the high (mark condition) state, and the
transmitter-empty bit (TxEMP) in the USR is set. Transmission resumes and the TxEMP
bit is cleared when the CPU loads a new character into the UART transmitter buffer (UTB).
If the transmitter receives a Disable command, it continues operating until the character
(if one is present) in the transmit-shift register is completely shifted out of transmitter TxD.
If the transmitter is reset through a software command, operation ceases immediately
(refer to subsection Section 12.4.1.5 Command Register (UCR)). The transmitter is re-
enabled through the UCR to resume operation after a disable or software reset.
If clear-to-send operation is enabled, CTS must be asserted for the character to be
transmitted. If CTS is negated in the middle of a transmission, the character in the shift
register is transmitted and following the completion of STOP bits TxD, enters in the mark
state until CTS is asserted again. If the transmitter is forced to send a continuous low
condition by issuing a Send-Break command, the transmitter ignores the state of CTS.
You can program the transmitter to automatically negate the request-to-send (RTS
)
output on completion of a message transmission. If the transmitter is programmed to
operate in this mode, RTS
must be manually asserted before a message is transmitted.
In applications where the transmitter is disabled after transmission is complete and RTS
is appropriately programmed, RTS
is negated one bit time after the character in the shift
register is completely transmitted. You must manually enable the transmitter by setting the
enable-transmitter bit in the UART Command Register (UCR).
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...