Datasheet

UART Modules
MOTOROLA MCF5206e USER’S MANUAL 12-9
12.3.2.2 RECEIVER. The receiver is enabled through the UCR located within the UART
module. Functional timing information for the receiver is shown in Figure 12-6. The
receiver looks for a high-to-low (mark-to-space) transition of the start bit on RxD. When a
transition is detected, the state of RxD is sampled each 16× clock for eight clocks, starting
one-half clock after the transition (asynchronous operation) or at the next rising edge of
the bit time clock (synchronous operation). If RxD is sampled high, the start bit is not valid
and the search for the valid start bit repeats. If RxD is still low, a valid start bit is assumed
and the receiver continues to sample the input at one-bit time intervals at the theoretical
center of the bit.
This process continues until the proper number of data bits and parity (if any) is
assembled and one stop bit is detected. Data on the RxD input is sampled on the rising
edge of the programmed clock source. The least significant bit is received first. The data
is then transferred to a receiver holding register and the RxRDY bit in the USR is set. If
the character length is less than eight bits, the most significant unused bits in the receiver
holding register are cleared. The Rx RDY bit in the USR is set at the one-half point of the
stop bit.
After the stop bit is detected, the receiver immediately looks for the next start bit. However,
if a nonzero character is received without a stop bit (framing error) and RxD remains low
for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new
start bit is detected. The parity error (PE), framing error (FE), overrun error (OE), and
received break (RB) conditions (if any) set error and break flags in the USR at the received
character boundary and are valid only when the RxRDY bit in the USR is set.
If a break condition is detected (RxD is low for the entire character including the stop bit),
a character of all zeros is loaded into the receiver holding register and the Receive Break
(RB) and RxRDY bits in the USR are set. The RxD signal must return to a high condition
for at least one-half bit time before a search for the next start bit begins.
The receiver will detect the beginning of a break in the middle of a character if the break
persists through the next character time. When the break begins in the middle of a
character, the receiver places the damaged character in the receiver first-in-first-out
(FIFO) stack and sets the corresponding error conditions and RxRDY bit in the USR. The
break persists until the next character time, the receiver places an all-zero character into
the receiver FIFO, and sets the corresponding RB and RxRDY bits in the USR. Interrupts
can be enabled on receive break.
Fr
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Freescale Semiconductor, Inc.
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