Datasheet

MOTOROLA MCF5206e USER’S MANUAL 1-1
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SECTION 1
INTRODUCTION
1.1 BACKGROUND
The MCF5206e integrated microprocessor combines a Version 2 (V2) ColdFire
®
processor
core with several peripheral functions such as a DRAM controller, timers, general-purpose
I/O and serial interfaces, debug module, and system integration. Designed for embedded
control applications, the V2 ColdFire core delivers enhanced performance while maintaining
low system costs. To speed program execution, the largeon-chip instruction cache and
SRAM provide one-cycle access to critical code and data. The MCF5206e greatly reduces
the time required for system design and implementation by packaging common system
functions on chip and providing glueless interfaces to 8 bit, 16 bit, and 32 bit DRAM, SRAM,
ROM, and I/O devices.
The MCF5206e is an enhanced version of the MCF5206 processor, with the same
peripheral set, DMA, MAC, Hardware Divide, larger cache, and larger SRAM. It is pin
compatible with the MCF5206, with the DMA pins muxed with Timer 0 pins. Available in
3.3V, with 5V- tolerant I/O, at speeds of 45 MHz and 54 MHz; higher performance at a lower
price.
The revolutionary ColdFire microprocessor architecture gives cost-sensitive, high-volume
markets new levels of price and performance. Based on the concept of variable-length RISC
technology, ColdFire combines the architectural simplicity of conventional 32 bit RISC with
a memory-saving, variable-length instruction set. In defining the ColdFire architecture for
embedded processing applications, Motorola incorporated RISC architecture for peak
performance and a simplified version of the variable-length instruction set found in the
M68000 Family for code density and programmer familiarity.
By incorporating a variable-length instruction set architecture, embedded processor
designers using ColdFire processors will enjoy significant system-level advantages over
conventional 32-bit fixed-length RISC architectures. The denser binary code for ColdFire
processors consumes less valuable memory than any 32-bit fixed-length instruction set
RISC processor available. This improved code density means more efficient system
memory use for a given application and requires slower, less costly memory to help achieve
a target performance level.
The integrated peripheral functions provide high performance and flexibility. For starters, the
DRAM controller supports as much as 512 Mbytes of DRAM. The MCF5206e supports both
page-mode and extended-data-out DRAMs. Two channels of DMA allow for fast data
transfer using a programmable burst mode independent of processor execution. The serial
interfaces consist of two programmable full duplex UARTs and a separate I
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Motorola bus (M-Bus interface). The two 16-bit general-purpose multimode timers provide
Fr
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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