Datasheet

UART Modules
12-14 MCF5206e USER’S MANUAL MOTOROLA
12.3.4 Multidrop Mode
You can program the UART to operate in a wakeup mode for multidrop or multiprocessor
applications. Functional timing information for the multidrop mode is shown in Figure 12-
8. You select the mode by setting bits 3 and 4 in UART mode register 1 (UMR1). This
mode of operation connects the master station to several slave stations (maximum of
256). In this mode, the master transmits an address character followed by a block of data
characters targeted for one of the slave stations. The slave stations channel receivers are
disabled; however, they continuously monitor the data stream sent out by the master
station. When the master sends an address character, the slave receiver channel notifies
its respective CPU by setting the RxRDY bit in the USR and generating an interrupt (if
programmed to do so). Each slave station CPU then compares the received address to
its station address and enables its receiver if it wants to receive the subsequent data
characters or block of data from the master station. Slave stations not addressed continue
to monitor the data stream for the next address character. Data fields in the data stream
are separated by an address character. After a slave receives a block of data, the slave
station CPU disables the receiver and reinitiates the process.
A transmitted character from the master station consists of a start bit, a programmed
number of data bits, an address/data (A/D) bit flag, and a programmed number of stop
bits. The A/D bit identifies the type of character being transmitted to the slave station. The
character is interpreted as an address character if the A/D bit is set or as a data character
if the A/D bit is cleared. You select the polarity of the A/D bit by programming bit 2 of
UMR1. You should also program UMR1 before enabling the transmitter and loading the
corresponding data bits into the transmit buffer.
In multidrop mode, the receiver continuously monitors the received data stream,
regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the
RxRDY bit and loads the character into the receiver holding register FIFO stack, provided
the received A/D bit is a one (address tag). The character is discarded if the received
A/D bit is a zero (data tag). If the receiver is enabled, all received characters are
transferred to the CPU via the receiver holding register stack during read operations.
In either case, the data bits are loaded into the data portion of the stack while the A/D bit
is loaded into the status portion of the stack normally used for a parity error (USR bit 5).
Framing error, overrun error, and break detection operate normally. The A/D bit takes the
place of the parity bit; therefore, parity is neither calculated nor checked. Messages in this
mode can still contain error detection and correction information. One way to provide error
detection, if 8-bit characters are not required, is to use software to calculate parity and
append it to the 5-, 6-, or 7-bit character.
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Freescale Semiconductor, Inc.
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