Datasheet

UART Modules
12-16 MCF5206e USER’S MANUAL MOTOROLA
12.3.5 Bus Operation
This subsection describes the operation of the bus during read, write, and interrupt-
acknowledge cycles to the UART module. All UART module registers must be accessed
as bytes.
12.3.5.1 READ CYCLES. The CPU with zero wait states accesses the UART module
because the MCF5206e system clock is also used for the UART module. The UART
module responds to reads with byte data on D[7:0]. Reserved registers return logic zero
during reads.
12.3.5.2 WRITE CYCLES. The CPU with zero wait states accesses the UART module.
The UART module accepts write data on D[7:0]. Write cycles to read-only registers and
reserved registers complete in a normal manner without exception processing; however,
the data is ignored.
12.3.5.3 INTERRUPT ACKNOWLEDGE CYCLES. The UART module can arbitrate for
interrupt servicing and supply the interrupt vector when it has successfully won arbitration.
The vector number must be provided if interrupt servicing is necessary; thus, the interrupt
vector register (UIVR) must be initialized. The interrupt vector number generated by the
IVR is used if the autovector is not enabled in the SIM Interrupt Control Register (ICR). If
the UIVR is not initialized and the ICR is not programmed for autovector, a spurious
interrupt exception is taken if interrupts are generated. This works in conjunction with the
MCF5206e interrupt controller, which allows a programmable Interrupt Priority Level (IPL)
for the interrupt.
12.4 REGISTER DESCRIPTION AND PROGRAMMING
This subsection contains a detailed description of each register and its specific function
as well as flowcharts of basic UART module programming.
12.4.1 Register Description
Writing control bytes into the appropriate registers controls the UART operation. A list of
UART module registers and their associated addresses is shown in Table 12-1.
NOTE
All UART module registers are accessible only as bytes. You
should change the contents of the mode registers (UMR1 and
UMR2), clock-select register (UCSR), and the auxiliary control
register (UACR) bit 7 only after the receiver/transmitter is
issued a software RESET command—i.e., channel operation
must be disabled. You should be careful if the register
contents are changed during receiver/transmitter operations
as unpredictable results can occur.
For the registers discussed in the following pages, the numbers above the register
description represent the bit position in the register. The register description contains the
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