Datasheet

UART Modules
MOTOROLA MCF5206e USER’S MANUAL 12-19
“Force parity low” means forcing a 0 parity bit. “Force parity high” forces a 1 parity bit.
B/C1–B/C0 — Bits per Character
These bits select the number of data bits per character to be transmitted. The character
length listed in Table 12-3 does not include start, parity, or stop bits.
12.4.1.2 MODE REGISTER 2 (UMR2). UMR2 controls some of the UART module
configuration. It is accessed when the mode register pointer points to UMR2, which occurs
after any access to UMR1. Accesses to UMR2 do not change the pointer.
CM1–CM0 — Channel Mode
These bits select a channel mode as listed in Table 12-4. See Section 12.3.3 Looping
Modes for more information on the individual modes.
TxRTS — Transmitter Ready-to-Send
This bit controls the negation of the RTS signal.
In applications where the transmitter is disabled after transmission is complete, setting
this bit causes the OP bit to be cleared automatically one bit time after the characters (if
any) in the channel transmit shift register and the transmitter holding register are
completely transmitted, including the programmed number of stop bits. This feature
automatically terminates message transmission. You can perform this process by
following these steps:
Table 12-3. B/Cx Control Bits
B/C1 B/C0 BITS/CHARACTER
00 5 Bits
01 6 Bits
10 7 Bits
11 8 Bits
UMR2 MBAR + $180
7 6 5 4 3 2 1 0
CM1 CM0
TXRT
S
TXCT
S
SB3 SB2 SB1 SB0
RESET:
0 0 0 0 0 0 0 0
READ/WRITE SUPERVISOR OR USER
Table 12-4. CMx Control Bits
CM1 CM0 MODE
00 Normal
0 1 Automatic Echo
1 0 Local Loopback
1 1 Remote Loopback
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Freescale Semiconductor, Inc.
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