Datasheet

Introduction
1-2 MCF5206e USER’S MANUAL MOTOROLA
2
3
4
6
7
8
9
1
11
12
13
14
15
16
separate input and output signals. For system protection, the processor includes a
programmable 16-bit software watchdog timer and several bus monitors. In addition,
common system functions such as chip selects, interrupt control, bus arbitration, and IEEE
1149.1 Test (JTAG) support are included.
A sophisticated debug interface supports both background-debug mode and real-time trace.
This interface is common to all ColdFire processors and allows common emulator support
across the entire ColdFire Family.
1.2 MCF5206E FEATURES
The primary features of the MCF5206e integrated processor include the following:
• Version 2 ColdFire Processor Core
— Variable-length RISC
— 32-bit data bus
— 16 user-visible 32-bit registers
— Supervisor / User modes for system protection
— Vector base register to relocate exception vector table
— Optimized for high-level language constructs
— 50 MIPS at 54MHz
• Multiply/Accumulate Unit
— Provides high-speed, complex arithmetic processing for simple signal processing
applications
— 1 clock issue with 3-stage execute pipeline
— Supports both 16x16 multiplies and 32x32 multiplies with 32-bit accumulate
• 4 KByte Direct-Mapped Instruction Cache
— Provides one-cycle access to critical code
• 8 KByte On-Chip SRAM
— Provides one-cycle access to critical code and data
• Hardware Divide Module
— Supported divide functions include:
• 32/16, producing a 16-bit quotient and 16-bit remainder;
• 32/32, producing a 32-bit quotient;
• 32/32, producing a 32-bit remainder.
• DRAM Controller
— Programmable refresh timer provides CAS-before-RAS refresh
— Support for 2 separate memory banks
— Support for page-mode DRAMs and extended-data-out (EDO) DRAMs
— Allows external bus master access
1.
I
2
C is a proprietary Philips interface bus.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...