Datasheet

UART Modules
MOTOROLA MCF5206e USER’S MANUAL 12-21
12.4.1.3 STATUS REGISTER (USR). The USR indicates the status of the characters in
the receive FIFO and the status of the transmitter and receiver. The RB, FE, and PE bits
are cleared by the Reset Error Status command in the UCR if the RB bit has not been
read. Also, RB, FE, PE and OE can also be cleared by reading the Receive buffer (RE).
RB — Received Break
1 = An all-zero character of the programmed length has been received without a stop
bit. The RB bit is valid only when the RxRDY bit is set. A single FIFO position is
occupied when a break is received. Additional entries into the FIFO are inhibited
until RxD returns to the high state for at least one-half bit time, which is equal to
two successive edges of the internal or external clock x 1 or 16 successive edges
of the external clock x 16. The received break circuit detects breaks that originate
in the middle of a received character. However, if a break begins in the middle of
a character, it must persist until the end of the next detected character time.
0 = No break has been received.
Table 12-5. SBx Control Bits
SB3 SB2 SB1 SB0 LENGTH 6-8 BITS LENGTH 5 BITS
0 0 0 0 0.563 1.063
0 0 0 1 0.625 1.125
0 0 1 0 0.688 1.188
0 0 1 1 0.750 1.250
0 1 0 0 0.813 1.313
0 1 0 1 0.875 1.375
0 1 1 0 0.938 1.438
0 1 1 1 1.000 1.500
1 0 0 0 1.563 1.563
1 0 0 1 1.625 1.625
1 0 1 0 1.688 1.688
1 0 1 1 1.750 1.750
1 1 0 0 1.813 1.813
1 1 0 1 1.875 1.875
1 1 1 0 1.938 1.938
1 1 1 1 2.000 2.000
USR MBAR + $184
7 6 5 4 3 2 1 0
RB FE PE OE TXEMP TXRDY FFULL RXRDY
RESET:
0 0 0 0 0 0 0 0
READ ONLY SUPERVISOR OR USER
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