Datasheet

UART Modules
12-28 MCF5206e USER’S MANUAL MOTOROLA
while the receiver shifts and updates from the bottom of the stack when the shift register
has been filled (see Figure 12-4).
RB7–RB0 — These bits contain the character in the receiver buffer.
12.4.1.7 TRANSMITTER BUFFER (UTB). The transmitter buffer consists of two
registers: the transmitter-holding register and the transmitter shift register (see Figure 12-
4). The holding register accepts characters from the bus master if the TxRDY bit in the
channel's USR is set. A write to the transmitter buffer clears the TxRDY bit, inhibiting
additional characters until the shift register is ready to accept more data. When the shift
register is empty, it checks the holding register for a valid character to be sent (TxRDY bit
cleared). If a valid character is present, the shift register loads the character and reasserts
the TxRDY bit in the USR. Writes to the transmitter buffer when the channel's UART
Status Register (USR) TxRDY bit is clear and when the transmitter is disabled have no
effect on the transmitter buffer.
TB7–TB0 — These bits contain the character in the transmitter buffer.
12.4.1.8 INPUT PORT CHANGE REGISTER (UIPCR). The UIPCR shows the current
state and the change-of-state for the CTS
pin.
URB MBAR + $18C
7 6 5 4 3 2 1 0
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
RESET:
1 1 1 1 1 1 1 1
READ ONLY SUPERVISOR OR USER
UTB MBAR + $18C
7 6 5 4 3 2 1 0
TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0
RESET:
0 0 0 0 0 0 0 0
WRITE ONLY SUPERVISOR OR USER
UIPCR MBAR + $190
7 6 5 4 3 2 1 0
0 0 0 COS 1 1 1 CTS
RESET:
0 0 0 0 1 1 1 1
READ ONLY SUPERVISOR OR USER
Fr
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Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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