Datasheet

UART Modules
MOTOROLA MCF5206e USER’S MANUAL 12-29
Bits 7, 6, 5, 3, 2, 1 — Reserved by Motorola.
COS — Change-of-State
1 = A change-of-state (high-to-low or low-to-high transition), lasting longer than 25–
50 µs has occurred at the CTS input. When this bit is set, you can program the
UART Auxiliary Control Register (UACR) to generate an interrupt to the CPU.
0 = No change-of-state has occurred since the last time the CPU read the UART
Input Port Change Register (UIPCR). A read of the UIPCR also clears the UART
Interrupt Status Register (UISR)COS bit.
CTS — Current State
Starting two serial clock periods after reset, the CTS bit reflects the state of the CTS pin.
If the CTS pin is detected as asserted at that time, the COS bit is set, which initiates an
interrupt if the Input Enable Control (IEC) bit of the UACR register is enabled.
1 = The current state of the CTS input is logic one.
0 = The current state of the CTS input is logic zero.
12.4.1.9 AUXILIARY CONTROL REGISTER (UACR).
IEC — Input Enable Control
1 = UISR bit 7 is set and generates an interrupt when the COS bit in the UART Input
Port Change Register (UIPCR) is set by an external transition on the CTS input
(if bit 7 of the interrupt mask register (UIMR) is set to enable interrupts).
0 = Setting the corresponding bit in the UIPCR has no effect on UISR bit 7.
12.4.1.10 INTERRUPT STATUS REGISTER (UISR). The UISR provides enables for all
potential interrupt sources. The UART Interrupt Mask Register (UIMR) masks the
contents of this register. If a flag in the UISR is set and the corresponding bit in UIMR is
also set, the internal interrupt output is asserted. If the corresponding bit in the UIMR is
cleared, the state of the bit in the UISR has no effect on the interrupt output.
UACR MBAR + $190
7 6 5 4 3 2 1 0
- - - - - - - IEC
RESET:
0 0 0 0 0 0 0 0
WRITE ONLY SUPERVISOR OR USER
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