Datasheet

UART Modules
12-30 MCF5206e USER’S MANUAL MOTOROLA
NOTE
The UIMR does not mask reading of the UISR. True status is
provided regardless of the contents of UIMR. A UART module
reset clears the contents of UISR.
COS — Change-of-State
1 = A change-of-state has occurred at the CTS input and has been selected to cause
an interrupt by programming bit 0 of the UACR.
0 = COS bit in the UIPCR is not selected.
DB — Delta Break
1 = The receiver has detected the beginning or end of a received break.
0 = No new break-change condition to report. Refer to Section 12.4.1.5 Command
Register (UCR) for more information on the reset break-change interrupt
command.
RxRDY — Receiver Ready or FIFO Full
UMR1 bit 6 programs the function of this bit. It is a duplicate of either the FFULL or
RxRDY bit of USR.
TxRDY — Transmitter Ready
This bit is the duplication of the TxRDY bit in USR.
1 = The transmitter holding register is empty and ready to be loaded with a
character.
0 = The CPU loads the transmitter-holding register or the transmitter is disabled.
Characters loaded into the transmitter-holding register when TxRDY=0 are not
transmitted.
12.4.1.11 INTERRUPT MASK REGISTER (UIMR). The UIMR selects the
corresponding bits in the UISR that cause an interrupt. By setting the bit, the interrupt is
enabled. If one of the bits in the UISR is set and the corresponding bit in the UIMR is also
set, the internal interrupt output is asserted. If the corresponding bit in the UIMR is zero,
UISR MBAR + $194
7 6 5 4 3 2 1 0
COS — — — — DB RXRDY TXRDY
RESET:
0 0 0 0 0 0 0 0
READ ONLY SUPERVISOR OR USER
Fr
eescale S
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Freescale Semiconductor, Inc.
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