Datasheet

UART Modules
MOTOROLA MCF5206e USER’S MANUAL 12-31
the state of the bit in the UISR has no effect on the interrupt output. The UIMR does not
mask the reading of the UISR.
COS — Change-of-State
1 = Enable interrupt
0 = Disable interrupt
DB — Delta Break
1 = Enable interrupt
0 = Disable interrupt
FFULL — FIFO Full
1 = Enable interrupt
0 = Disable interrupt
TxRDY — Transmitter Ready
1 = Enable interrupt
0 = Disable interrupt
12.4.1.12 TIMER UPPER PRELOAD REGISTER 1 (UBG1). This register holds the
eight most significant bits of the preload value the timer uses for providing a given baud
rate. The minimum value that can be loaded on the concatenation of UBG1 with UBG2 is
$0002. This register is write only and cannot be read by the CPU.
12.4.1.13 TIMER UPPER PRELOAD REGISTER 2 (UBG2). This register holds the
eight least significant bits of the preload value the timer uses for providing a given baud
rate. The minimum value that can be loaded on the concatenation of UBG1 with UBG2 is
$0002. This register is write only and cannot be read by the CPU.
12.4.1.14 INTERRUPT VECTOR REGISTER (UIVR). The UIVR contains the 8-bit
vector number of the internal interrupt.
UIMR MBAR + $194
7 6 5 4 3 2 1 0
COS — — — — DB FFULL TXRDY
RESET:
0 0 0 0 0 0 0 0
WRITE ONLY SUPERVISOR OR USER
UIVR MBAR + $1B0
7 6 5 4 3 2 1 0
IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0
RESET:
0 0 0 0 1 1 1 1
READ/WRITE SUPERVISOR OR USER
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