Datasheet

UART Modules
12-32 MCF5206e USER’S MANUAL MOTOROLA
IVR7–IVR0 — Interrupt Vector Bits
This 8-bit number indicates the offset from the base of the vector table where the address
of the exception handler for the specified interrupt is located. The UIVR is reset to $0F,
which indicates an uninitialized interrupt condition.
12.4.1.14.1 Input Port Register (UIP). The UIP register shows the current state of the
CTS input.
CTS — Current State
1 = The current state of the CTS input is logic one.
0 = The current state of the CTS input is logic zero.
The information contained in this bit is latched and reflects the state of the input pin at the
time that the UIP is read.
NOTE
This bit has the same function and value as the UIPCR bit 0.
12.4.1.14.2 Output Port Data Registers (UOP1, UOP0). The RTS output is set by a bit
set command (writing to UOP1) and is cleared by a bit reset command (writing to UOP0).
RTS
— Output Port Parallel Output
1 = A write cycle to the OPset address asserts the RTS
signal.
0 = This bit is not affected by writing a zero to this address.
NOTE
The output port bits are inverted at the pins so the RTS set bit
provides an asserted RTS pin.
UIP MBAR + $1B4
7 6 5 4 3 2 1 0
— — — — — — — CTS
RESET:
1 1 1 1 1 1 1 1
READ ONLY SUPERVISOR OR USER
UOP1 MB AR + $148
7 6 5 4 3 2 1 0
RTS
RESET:
— — — — — — — 0
WRITE ONLY SUPERVISOR OR USER
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...