Datasheet

M-Bus Module
13-4 MCF5206e USER’S MANUAL MOTOROLA
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In addition, if the MCF5206e is master, it must not transmit an address that is equal to its
slave address. The MCF5206e cannot be master and slave at the same time.
Only the slave with a calling address that matches the one transmitted by the master will
responds by returning an acknowledge bit by pulling the SDA low at the 9th clock (see Figure
13-2).
13.4.3 Data Transfer
Once successful slave addressing is achieved, the data transfer can proceed on a byte-by-
byte basis in the direction specified by the R/W bit sent by the calling master.
Each data byte is 8 bits long. Data can be changed only while SCL is low and must be held
stable while SCL is high, as shown in Figure 13-2. There is one clock pulse on SCL for each
data bit with the MSB being transferred first. Each byte data must be followed by an
acknowledge bit, which is signalled from the receiving device by pulling the SDA low at the
ninth clock. One complete data byte transfer needs nine clock pulses.
If the slave receiver does not acknowledge the master, the SDA line must be left high by the
slave. The master can then generate a stop signal to abort the data transfer or a start signal
(repeated start) to commence a new calling.
If the master receiver does not acknowledge the slave transmitter after a byte transmission,
it means'‘end of data'’ to the slave. The slave releases the SDA line for the master to
generate STOP or START signal.
13.4.4 Repeated START Signal
As shown in Figure 13-2, a repeated START signal is a START signal generated without first
generating a STOP signal to terminate the communication. The master uses this method to
communicate with another slave or with the same slave in different mode (transmit/receive
mode) without releasing the bus.
13.4.5 STOP Signal
The master can terminate the communication by generating a STOP signal to free the bus.
However, the master can generate a repeated START by issuing a START signal followed
by a calling command without generating a STOP signal first. This is called repeated
START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical “1”
(see Figure 13-2). Note that a master can generate a STOP even if the slave has done an
acknowledgment at which point the slave must release the bus.
13.4.6 Arbitration Procedure
M-Bus is a true multimaster bus that allows more than one master to be connected on it. If
two or more masters try to simultaneously control the bus, a clock synchronization
procedure determines the bus clock, for which the low period is equal to the longest clock
low period and the high is equal to the shortest one among the masters. A data arbitration
procedure determines the relative priority of the contending masters. A bus master loses
arbitration if it transmits logic “1” while another master transmits logic “0.” The losing masters
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