Datasheet

M-Bus Module
13-6 MCF5206e USER’S MANUAL MOTOROLA
2
4
5
6
7
8
9
10
11
12
13
14
15
16
1
then release it. If the slave SCL low period is greater than the master SCL low period, the
resulting SCL bus signal low period is stretched.
13.5 PROGRAMMING MODEL
Five registers are used in the M-Bus interface and the internal configuration of these
registers is discussed in the following paragraphs.The programmer’s model of the M-Bus
interface is shown below in Table 13-1.
A block diagram of the M-Bus system is shown in Figure 13-1.
13.5.1 M-Bus Address Register (MADR)
This register contains the address the M-Bus responds to when addressed as a slave; note
that it is not the address sent on the bus during the address transfer.
ADR7–ADR1 — Slave Address
Bit 1 to bit 7 contain the specific slave address to be used by the M-Bus module.
NOTE
The default mode of M-Bus is slave mode for an address match
on the bus.
13.5.2 M-Bus Frequency Divider Register (MFDR)
MBC5–MBC0 — M-Bus Clock Rate 5–0
This field is used to prescale the clock for bit rate selection. Due to the potential slow rise
and fall times of the SCL and SDA signals, the bus signals are sampled at the prescaler
Table 13-1. M-Bus Interface Programmer’s Model
ADDRESS M-BUS MODULE REGISTERS
MBAR+$1E0 M-Bus Address register (MADR)
MBAR+$1E4 M-Bus Frequency Divider Register (MFDR)
MBAR+$1E8 M-Bus Control Register (MBCR)
MBAR+$1EC M-Bus Status Register (MBSR)
MBAR+$1F0 M-Bus Data I/O Register (MBDR)
M-Bus Address Register (MADR) Address MBAR+$1E0
7 6 5 4 3 2 1 0
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 -
RESET 0 0 0 0 0 0 0 0
Read/Write Supervisor or User Mode
M-Bus Frequency Divider Register
(MFDR)
Address MBAR+$1E4
7 6 5 4 3 2 1 0
- - MBC5 MBC4 MBC3 MBC2 MBC1 MBC0
RESET 0 0 0 0 0 0 0 0
Read/Write Supervisor or User Mode
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...