Datasheet

M-Bus Module
13-8 MCF5206e USER’S MANUAL MOTOROLA
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13.5.3 M-Bus Control Register (MBCR)
MEN — M-Bus Enable
This bit controls the software reset of the entire M-Bus module.
1 = The M-Bus module is enabled. This bit must be set before any other MBCR bits
have any effect.
0 = The module is reset and disabled. This is the power-on reset situation. When low,
the interface is held in reset but registers can still be accessed.
If the M-Bus module is enabled in the middle of a byte transfer, the interface behaves as
follows: the slave mode ignores the current transfer on the bus and starts operating
whenever a subsequent start condition is detected. Master mode will not be aware that the
bus is busy; therefore, if a start cycle is initiated, the current bus cycle can become corrupt.
This would ultimately result in either the current bus master or the M-Bus module losing
arbitration, after which bus operation would return to normal.
MIEN — M-Bus Interrupt Enable
1 = Interrupts from the M-Bus module are enabled. An M-Bus interrupt occurs provided
the MIF bit in the status register is also set.
0 = Interrupts from the M-Bus module are disabled. This does not clear any currently
pending interrupt condition.
MSTA — Master/Slave Mode Select Bit
At reset, this bit is cleared. When this bit is changed from 0 to 1, a START signal is generated
on the bus, and the master mode is selected. When this bit is changed from 1 to 0, a STOP
signal is generated and the operation mode changes from master to slave.
MSTA is cleared without generating a STOP signal when the master loses arbitration.
1 = Master Mode
0 = Slave Mode
MTX — Transmit/Receive mode select bit
This bit selects the direction of master and slave transfers. When addressed as a slave this
bit should be set by software according to the SRW bit in the status register. In master mode,
this bit should be set according to the type of transfer required. Therefore, for address
cycles, this bit is always high.
1 = Transmit
0 = Receive
M-Bus Control Register (MBCR) Address MBAR+$1E8
7 6 5 4 3 2 1 0
MEN MIEN MSTA MTX TXAK RSTA -
RESET 0 0 0 0 0 0 0 0
Read/Write Supervisor or User Mode
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Freescale Semiconductor, Inc.
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