Datasheet

M-Bus Module
MOTOROLA MCF5206e USER’S MANUAL 13-9
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TXAK — Transmit Acknowledge Enable
This bit specifies the value driven onto SDA during acknowledge cycles for both master and
slave receivers. Note that writing this bit only applies when the M-Bus is a receiver, not a
transmitter.
1 = No acknowledge signal response is sent (i.e., acknowledge bit = 1)
0 = An acknowledge signal is sent out to the bus at the 9th clock bit after receiving one
byte data
RSTA — Repeat Start
Writing a 1 to this bit generates a repeated START condition on the bus, provided it is the
current bus master. This bit is always read as a low. Attempting a repeated start when the
bus is owned by another master results in loss of arbitration. Note that this bit is not
readable.
1 = Generate repeat start cycle
13.5.4 M-Bus Status Register (MBSR)
This status register is read-only with the exception of bit 1 (MIF) and bit 4 (MAL), which can
be cleared by software. All bits are cleared on reset except bit 7 (MCF) and bit 0 (RXAK),
which are set (=1) at reset.
MCF — Data Transferring Bit
While one byte of data is being transferred, this bit is cleared. It is set by the falling edge of
the 9th clock of a byte transfer.
1 = Transfer complete
0 = Transfer in progress
MAAS — Addressed as a Slave Bit
When its own specific address (M-Bus Address Register) is matched with the calling
address, this bit is set. The CPU is interrupted provided the MIEN is set. Next, the CPU must
check the SRW bit and set its TX/RX mode accordingly.
Writing to the M-Bus Control Register clears this bit.
1 = Addressed as a slave
0 = Not addressed
M-Bus Status Register (MBSR) Address MBAR+$1EC
7 6 5 4 3 2 1 0
MCF MAAS MBB MAL - SRW MIF RXAK
RESET 1 0 0 0 0 0 0 1
Read/Write Supervisor or User Mode
Fr
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Freescale Semiconductor, Inc.
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