Datasheet

Introduction
MOTOROLA MCF5206e USER’S MANUAL 1-5
provide an overview of the integrated processor.
Figure 1-1. MCF5206e Block Diagram
1.3.1 ColdFire Processor Core
The ColdFire processor core consists of two independent, decoupled pipeline structures to
maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a
two-stage pipeline for prefetching instructions. The prefetched instruction stream is then
gated into the two-stage operand execution pipeline (OEP), which decodes the instruction,
fetches the required operands and then executes the required function. Because the IFP
and OEP pipelines are decoupled by an instruction buffer that serves as a FIFO queue, the
IFP can prefetch instructions in advance of their actual use by the OEP, thereby minimizing
time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline
featuring a traditional RISC datapath with a dual-read-ported register file feeding an
arithmetic/logic unit. The MCF5206e also includes MAC and hardware divide instructions
which enhance the mathematical performance.
DRAM
CHIP
INTERRUPT
CONTROLLER
EXTERNAL
DRAM
CONTROL
CHIP
SELECTS
INTERRUPT
SUPPORT
SERIAL
INTERFACE
CLOCK
INPUT
PARALLEL
TIMER
SUPPORT
BDM
INTERFACE
BUS INTERFACE
CONTROLLER
SELECTS
PARALLEL
PORT
UARTS
TIMERS
M-BUS
MODULE
4 KBYTE ICACHE
COLDFIRE
8 KBYTE SRAM
V2 CORE
JTAG
SYSTEM BUS
CONTROLLER
JTAG
INTERFACE
INTERFACE
M-BUS
INTERFACE
CLOCK
EXTERNAL
BUS
DMA
MODULE
DMA
INTERFACE
MAC MODULE
H/W DIVIDE MODULE
DEBUG
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...