Datasheet

M-Bus Module
13-10 MCF5206e USER’S MANUAL MOTOROLA
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MBB — Bus Busy Bit
This bit indicates the status of the bus. When a START signal is detected, the MBB is set. If
a STOP signal is detected, it is cleared.
1 = Bus is busy
0 = Bus is idle
MAL — Arbitration Lost
Hardware sets the arbitration lost bit (MAL) when the arbitration procedure is lost. Arbitration
is lost in the following circumstances:
1. SDA sampled as low when the master drives a high during an address or data-transmit
cycle.
2. SDA sampled as a low when the master drives a high during the acknowledge bit of a
data-receive cycle.
3. A start cycle is attempted when the bus is busy.
4. A repeated start cycle is requested in slave mode.
5. A stop condition is detected when the master did not request it.
This bit must be cleared by software by writing a low to it.
SRW — Slave Read/Write
When MAAS is set, this bit indicates the value of the R/W command bit of the calling address
sent from the master. This bit is valid only when 1) a complete transfer has occurred and no
other transfers have been initiated and 2) M-Bus is a slave and has an address match.
Checking this bit, the CPU can select slave transmit/receive mode according to the
command of the master.
1 = Slave transmit, master reading from slave
0 = Slave receive, master writing to slave
MIF — M-Bus Interrupt
The MIF bit is set when an interrupt is pending, which causes a processor interrupt request
(provided MIEN is set). MIF is set when one of the following events occurs:
1. Complete one byte transfer (set at the falling edge of the 9th clock)
2. Receive a calling address that matches its own specific address in slave-receive mode
3. Arbitration lost
This bit must be cleared by software by writing a low to it in the interrupt routine.
RXAK — Received Acknowledge
The value of SDA during the acknowledge bit of a bus cycle. If the received acknowledge bit
(RXAK) is low, it indicates an acknowledge signal has been received after the completion of
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