Datasheet

M-Bus Module
MOTOROLA MCF5206e USER’S MANUAL 13-11
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8 bits data transmission on the bus. If RXAK is high, it means no acknowledge signal has
been detected at the 9th clock.
1 = No acknowledge received
0 = Acknowledge received
13.5.5 M-Bus Data I/O Register (MBDR)
When an address and R/W bit is written to the MBDR and the M-Bus is the master, a
transmission starts. When data is written to the MBDR, a data transfer is initiated. The most
significant bit is sent first in both cases. In the master receive mode, reading the MBDR
register allows the read to occur but also initiates next byte data receiving. In slave mode,
the same function is available after it is addressed.
13.6 M-BUS PROGRAMMING EXAMPLES
13.6.1 Initialization Sequence
Reset will put the M-Bus Control Register to its default status. Before the interface can
transfer serial data, you must perform an initialization procedure as follows:
1. Update the Frequency Divider Register (MFDR) and select the required division ratio
to obtain SCL frequency from system clock.
2. Update the M-Bus Address Register (MADR) to define its slave address.
3. Set the MEN bit of the M-Bus Control Register (MBCR) to enable the M-Bus interface
system.
4. Modify the bits of the M-Bus Control Register (MBCR) to select master/slave mode,
transmit/receive mode, and interrupt enable or not.
13.6.2 Generation of START
After completion of the initialization procedure, you can transmit serial data by selecting the
'‘master transmitter'’ mode. If the device is connected to a multi-master bus system, you
must test the state of the M-Bus Busy Bit (MBB) to check whether the serial bus is free.
If the bus is free (MBB=0), the start condition and the first byte (the slave address) can be
sent. The data written to the data register comprises the slave-calling address and the LSB
set to indicate the direction of transfer required from the slave.
The bus free time (i.e., the time between a STOP condition and the following START
condition) is built into the hardware that generates the START cycle. Depending on the
relative frequencies of the system clock and the SCL period, you may have to wait until the
M-Bus Data I/O Register (MBDR) Address MBAR+$1F0
7 6 5 4 3 2 1 0
D7 D6 D5 D4 D3 D2 D1 D0
RESET 0 0 0 0 0 0 0 0
Read/Write Supervisor or User Mode
Fr
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Freescale Semiconductor, Inc.
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