Datasheet

M-Bus Module
13-14 MCF5206e USER’S MANUAL MOTOROLA
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; TRANSMITTING
BRANXMAR
ENMASRBCLR.B#5,MBCR; LAST ONE, GENERATE'STOP'
; SIGNAL
NXMARMOVE.BMBDR,RXBUF; READ DATA AND STORE
RTE
13.6.5 Generation of Repeated START
At the end of data transfer, if the master still wants to communicate on the bus, it can
generate another START signal followed by another slave address without first generating
a STOP signal. A program example is as shown.
RESTARTMOVE.BMBCR,-(A7); ANOTHER START (RESTART)
BSET.B#2, (A7)
MOVE.B(A7)+, MBCR
MOVE.BCALLING,-(A7); TRANSMIT THE CALLING
MOVE.BCALLING,-(A7); ADDRESS, D0=R/W-
MOVE.B(A7)+, MBDR
13.6.6 Slave Mode
In the slave interrupt service routine, the module addressed as slave bit (MAAS) should be
tested to check if a calling of its own address has just been received. If MAAS is set, software
should set the transmit/receive mode select bit (MTX bit of MBCR) according to the R/W
command bit (SRW). Writing to the MBCR clears the MAAS automatically. The only time
MAAS is read as set is from the interrupt at the end of the address cycle where an address
match occurred; interrupts resulting from subsequent data transfers have MAAS cleared. A
data transfer can now be initiated by writing information to MBDR, for slave transmits, or
dummy reading from MBDR, in slave-receive mode. The slave drives SCL low in between
byte transfers. SCL is released when the MBDR is accessed in the required mode.
In the slave transmitter routine, the received acknowledge bit (RXAK) must be tested before
transmitting the next byte of data. Setting RXAK means an '‘end-of-data’' signal from the
master receiver, after which it must be switched from transmitter mode to receiver mode by
software. A dummy read then releases the SCL line so that the master can generate a STOP
signal.
13.6.7 Arbitration Lost
If several masters try to simultaneously engage the bus, only one master wins and the
others lose arbitration. The devices that lost arbitration are immediately switched to slave
receive mode by the hardware. Their data output to the SDA line is stopped, but SCL is still
generated until the end of the byte during which arbitration was lost. An interrupt occurs at
the falling edge of the ninth clock of this transfer with MAL=1 and MSTA=0. If one master
tries to transmit or do a START while the bus is being engaged by another master, the
hardware will: (1) inhibit the transmission, (2) switch the MSTA bit from 1 to 0 without
generating STOP condition, (3) generate an interrupt to CPU and, (4) set the MAL to indicate
Fr
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Freescale Semiconductor, Inc.
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