Datasheet

Introduction
1-6 MCF5206e USER’S MANUAL MOTOROLA
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1.3.1.1 PROCESSOR STATES. The processor is always in one of four states: normal
processing, exception processing, stopped, or halted. It is in the normal processing state
when executing instructions, fetching instructions and operands, and storing instruction
results.
Exception processing is the transition from program processing to system, interrupt, and
exception handling. Exception processing includes fetching the exception vector, stacking
operations, and refilling the instruction fetch pipe after an exception. The processor enters
exception processing when an exceptional internal condition arises, such as tracing an
instruction, an instruction resulting in a trap, or executing specific instructions. External
conditions, such as interrupts and access errors, also cause exceptions. Exception
processing ends when the first instruction of the exception handler enters the operand
execution pipeline.
Stopped mode is a reduced power operation mode that causes the processor to remain
quiescent until either a reset or nonmasked interrupt occurs. The STOP instruction is used
to enter this operation mode.
The processor halts when it receives an access error or generates an address error while in
the exception processing state. For example, if during exception processing of one access
error another access error occurs, the MCF5206e processor cannot complete the transition
to normal processing nor can it save the internal machine state. The processor assumes that
the system is not operational and halts. Only an external reset can restart a halted
processor. When the processor executes a STOP instruction, it is in a special type of normal
processing state, e.g., one without bus cycles. The processor stops but it does not halt.
The processor can also halt in a restart mode because of background debug mode events.
1.3.1.2 PROGRAMMING MODEL. The ColdFire programming model is separated into two
privilege modes: supervisor and user. The S bit in the status register (SR) indicates the
current privilege mode. The processor identifies a logical address by accessing either the
supervisor or user address space, which differentiates between supervisor and user modes.
Programs access registers based on the indicated mode. User programs can access only
registers specific to the user mode. System software executing in the supervisor mode can
access all registers using the control registers to perform supervisory functions. User
programs are thus restricted from accessing privileged information. The operating system
performs management and service tasks for user programs by coordinating their activities.
This difference allows the supervisor mode to protect system resources from uncontrolled
accesses.
Most instructions execute in either mode but some instructions that have important system
effects are privileged and can execute only in the supervisor mode. For instance, user
programs cannot execute the STOP instructions. To prevent a program executing in user
mode from entering the supervisor mode, instructions that can alter the S bit in the SR are
privileged. The TRAP instructions provide controlled access to operating system services
for user programs.
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Freescale Semiconductor, Inc.
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