Datasheet

Timer Module
14-4 MCF5206e USER’S MANUAL MOTOROLA
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14.4.1.1 TIMER MODE REGISTER (TMR). TMR is a 16-bit memory-mapped register. This
register programs the various timer modes and is cleared by reset.
PS7–PS0 — Prescaler Value
The prescaler is programmed to divide the clock input by values from 1 to 256. The value
00000000 divides the clock by 1; the value 11111111 divides the clock by 256.
Prescalar value = $[PS7 - PS0] + 1
CE1–CE0 — Capture Edge and Enable Interrupt
11 = Capture on any edge and enable interrupt on capture event
10 = Capture on falling edge only and enable interrupt on capture event
01 = Capture on rising edge only and enable interrupt on capture event
00 = Disable interrupt on capture event
OM — Output Mode
1 = Toggle output
0 = Active-low pulse for one system clock cycle (18.5 ns at 54 MHz)
ORI — Output Reference Interrupt Enable
1 = Enable interrupt upon reaching the reference value
0 = Disable interrupt for reference reached (does not affect interrupt on capture
function)
NOTE
If ORI is set when the REF event is asserted in the Timer Event
Register (TER), an immediate interrupt occurs. If ORI is cleared
while an interrupt is asserted, the interrupt negates.
FRR — Free Run/Restart
1 = Restart: Timer count is reset immediately after reaching the reference value
0 = Free run: Timer count continues to increment after reaching the reference value
CLK1–CLK0 — Input Clock Source for the Timer
11 = TIN pin (falling edge)
10 = Master system clock divided by 16. Note that this clock source is not synchronized
to the timer; thus successive time-outs may vary slightly in length
01 = Master system clock
00 = Stops counter. After the counter is stopped, the value in the Timer Counter (TCN)
register remains constant.
Timer Mode Register (TMR) Address MBAR+$100, MBAR+$120
1514131211109876543210
PRESCALER VALUE (PS7 - PS0) CE1 - CE0 OM ORI FRR ICLK1 - ICLK0 RST
RESET0000000000000000
Read/Write Supervisor or User Mode
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