Datasheet

Timer Module
14-6 MCF5206e USER’S MANUAL MOTOROLA
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14.4.1.5 TIMER EVENT REGISTER (TER). The TER is an 8-bit register that reports events
the timer recognizes. When the timer recognizes an event, it sets the appropriate bit in the
TER, regardless of the corresponding interrupt-enable bits (ORI and CE) in the TMR.
TER appears as a memory-mapped register and can be read at any time.
You should write a one to a bit to clear it (writing a zero does not affect bit value); more than
one bit can be cleared at a time. The REF and CAP bits must be cleared before the timer
will negate the IRQ to the interrupt controller. Reset clears this register.
Bits 7–2 — Reserved for future use.
These bits are currently 0 when read.
CAP — Capture Event
If a one is read from this bit, the counter value has been latched into the TCR. The CE bit in
the TMR enables the interrupt request caused by this event. You should write a one to this
bit to clear the event condition.
REF — Output Reference Event
If a one is read from this bit, the counter has reached the TRR value. The ORI bit in the TMR
enables the interrupt request caused by this event. You should write a one to this bit to clear
the event condition.
Example code: Timer Initialization
There are two timers on the MCF5206e. With a 54MHZ clock, the maximum period is 5
seconds and a resolution of 18.5 ns. They can be free running or count to a value and reset.
The following examples set up the timers:
Timer 1 will count to $AFAF, toggle its output, and reset back to $0000. This will continue
infinitely until the timer is disabled or a reset occurs. No interrupts are set. Prescale is set at
256 and the system clock is divided by 16, therefore resolution is (16*(256))/25MHz =
163.84us. Timeout period is (16*256*44976)/25mhz = 7.369s. ($0 - $AFAF = 44976
decimal)
Timer 2 will be free-running and send out a logic pulse every time it compares the count
value in the TRR register. value, which for now, is randomly chosen as $1234. Prescale is
set at 127 with the sys_clock initially divided by 16 (by setting bits 2&1 of the TMR register
to 10 therefore, resolution is (16*(127))/25mhz = 81.28us. Interrupts are NOT enabled.
Timer Event Register (TER)
Address MBAR+$111,MBAR+$131
7 6 5 4 3 2 1 0
RESERVED READ AS 0 REF CAP
RESET 0 0 0 0 0 0 0 0
Read/Write Supervisor or User Mode
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