Datasheet

Debug Support
15-2 MCF5206e USER’S MANUAL MOTOROLA
The processor status timing is synchronous with the processor clock (CLK) and the status
may not be related to the current bus transfer. Table 15-1 below shows the encodings of
these signals.
The processor status outputs can be used with an external image of the program to
completely track the dynamic execution path of the machine. The tracking of this dynamic
path is complicated by any change-of-flow operation. Within the ColdFire instruction set
architecture, most branch instructions are implemented using PC-relative addressing.
Accordingly, the external program image can determine branch target addresses.
Additionally, there are a number of instructions that use some type of variant addressing,
i.e., the calculation of the target instruction address is not PC-relative or absolute but
involves the use of a program-visible register.
The simplest example of a branch instruction using a variant addressing mode is the
compiled code for a C language case statement. Typically, the evaluation of this statement
uses the variable of an expression as an index into a table of offsets, where each offset
points to a unique case within the structure. For these types of change-of-flow operations,
the ColdFire processor uses the debug pins to output a sequence of information.
1. Identify a taken branch has been executed using the PST[3:0]=$5.
2. Using the PST pins, signal the target address is to be displayed on the DDATA pins.
The encoding identifies the number of bytes that are displayed and is optional.
3. The new target address is optionally available on subsequent cycles using the nibble-
wide DDATA port. The number of bytes of the target address displayed on this port is
Table 15-1. Processor PST Definition
PST[3:0]
DEFINITION
(HEX) (BINARY)
$0 0000 Continue execution
$1 0001 Begin execution of an instruction
$2 0010 Reserved
$3 0011 Entry into user-mode
$4 0100 Begin execution of PULSE or WDDATA instruction
$5 0101 Begin execution of taken branch
$6 0110 Reserved
$7 0111 Begin execution of RTE instruction
$8 1000 Begin 1-byte transfer on DData
$9 1001 Begin 2-byte transfer on DData
$A 1010 Begin 3-byte transfer on DData
$B 1011 Begin 4-byte transfer on DData
$C 1100 † Exception processing
$D 1101 † Emulator-mode entry exception processing
$E 1110 † Processor is stopped, waiting for interrupt
$F 1111 † Processor is halted
† These encodings are asserted for multiple cycles.
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