Datasheet

Debug Support
MOTOROLA MCF5206e USER’S MANUAL 15-3
a configurable parameter (2, 3, or 4 bytes).
The nibble-wide DDATA port includes two 32-bit storage elements for capturing the CPU
core bus information. These two elements effectively form a FIFO buffer connecting the core
bus to the external development system. The FIFO buffer captures variant branch target
addresses along with certain operand read/write data for eventual display on the DDATA
output port. The execution speed of the ColdFire processor is affected only when both
storage elements contain valid data waiting to be dumped onto the DDATA port. In this case,
the processor core stalls until one FIFO entry is available. In all other cases, data output on
the DDATA port does not impact execution speed.
From the processor core perspective, the PST outputs signal the first AGEX cycle of an
instruction’s execution. Most single-cycle instructions begin and complete their execution
within a given machine cycle.
Because the processor status (PST[3:0]) values of $C, $D, $E, and $F define a multicycle
mode or a special operation, the PST outputs are driven with these values until the mode is
exited or the operation completed. All the remaining fields specify information that is updated
each machine cycle.
The status values of $8, $9, $A, and $B qualify the contents of the DDATA output bus. These
encodings are driven onto the PST port one machine cycle before the actual data is
displayed on DDATA.
Figure15-2 shows the execution of an indirect JMP instruction with the lower 16 bits of the
target address being displayed on the DDATA output. In this diagram, the indirect JMP
branches to address “target.” The processor internally forms the PST marker ($9) one cycle
before the address begins to appear on the DDATA port. The target address is displayed on
DDATA for four consecutive clocks, starting with the least-significant nibble. The processor
continues execution, unaffected by the DDATA bus activity.
Figure 15-2. Pipeline Timing Example (Debug Output)
The ColdFire instruction set architecture (ISA) includes a PULSE opcode. This opcode
generates a unique PST encoding when executed (PST = $4). This instruction can define
logic analyzer triggers for debug and/or performance analysis.
Last
DSOC AGEX
JMP (A0)
DSOC AGEX
Target
IAG IC DSOC AGEX
Target + $4
IAG IC DSOC AGEX
Internal PST
$5 $9 $0 TARGET
Internal DDATA
$0 $0 3:0 7:4 11:8 15:12
PST Pins
$5 $9 $0 TARGET
DDATA Pins
$0 $0 3:0 7:4 11:8 15:12
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