Datasheet

Debug Support
15-4 MCF5206e USER’S MANUAL MOTOROLA
Additionally, a WDDATA opcode is supported that lets the processor core write any operand
(byte, word, longword) directly to the DDATA port, independent of any Debug module
configuration. This opcode also generates the special PST = $4 encoding when executed.
15.2 BACKGROUND DEBUG MODE (BDM)
ColdFire 5200 processors support a modified version of the BDM functionality found on
Motorola’s CPU32 Family of parts. BDM implements a low-level system debugger in the
microprocessor hardware. Communication with the development system is handled via a
dedicated, high-speed serial command interface (BDM port).
Unless noted otherwise, the BDM functionality provided by ColdFire 5200 processors is a
proper subset of the CPU32 functionality. The main differences include the following:
• ColdFire implements the BDM controller in a dedicated hardware module. Although
some BDM operations do require the CPU to be halted (e.g., CPU register accesses),
other BDM commands such as memory accesses can be executed while the processor
is running.
•DSCLK, DSI, and DSO are treated as synchronous signals, where the inputs (DSCLK
and DSI) must meet the required input setup and hold timings, and the output (DSO) is
specified as a delay relative to the rising edge of the processor clock.
• On CPU32 parts, DSO could signal hardware that a serial transfer can start. ColdFire
clocking schemes restrict the use of this bit. Because DSO changes only when DSCLK
is high, DSO cannot be used to indicate the start of a serial transfer. The development
system should use either a free-running DSCLK or count the number of clocks in any
given transfer.
• The Read/Write System Register commands (RSREG/WSREG) have been replaced
by Read/Write Control Register commands (RCREG/WCREG). These commands use
the register coding scheme from the MOVEC instruction.
• Read/Write Debug Module Register commands (RDMREG/WDMREG) have been add-
ed to support Debug module register accesses.
• CALL and RST commands are not supported.
• Illegal command responses can be returned using the FILL and DUMP commands.
• For any command performing a byte-sized memory read operation, the upper 8 bits of
the response data are undefined. The referenced data is returned in the lower 8 bits of
the response.
• The debug module forces alignment for memory-referencing operations: long accesses
are forced to a 0-modulo-4 address; word accesses are forced to a 0-modulo-2
address. An address error response can no longer be returned.
15.2.1 CPU Halt
Although some BDM operations can occur in parallel with CPU operation, unrestricted BDM
operation requires the CPU to be halted. A number of sources can cause the CPU to halt,
including the following (as shown in order of priority):
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