Datasheet

Debug Support
15-6 MCF5206e USER’S MANUAL MOTOROLA
15.2.2 BDM Serial Interface
Once the CPU is halted and the halt status reflected on the PST outputs (PST[3:0]=$F), the
development system can send unrestricted commands to the Debug module. The Debug
module implements a synchronous protocol using a three-pin interface: development serial
clock (DSCLK), development serial input (DSI), and development serial output (DSO). The
development system serves as the serial communication channel master and is responsible
for generation of the clock (DSCLK). The operating range of the serial channel is DC to one-
half of the processor frequency. The channel uses a full duplex mode, where data is
transmitted and received simultaneously by both master and slave devices.
Figure 15-3. DBM Serial Transfer
Both DSCLK and DSI are synchronous inputs and must meet input setup and hold times
with respect to CLK. DSCLK essentially acts as a pseudo “clock enable” and is sampled on
the rising edge of CLK. If the setup time of DSCLK is met, then the internal logic transitions
on the rising edge of CLK, and DSI is sampled on the same CLK rising edge. The DSO
output is specified as a delay from the DSCLK-enabled CLK rising edge. All events in the
P
STCLK
D
SCLK
C
PU CLK
NEXT STATE
B
DM STATE
M
ACHINE
D
SO
D
SII
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