Datasheet

Debug Support
MOTOROLA MCF5206e USER’S MANUAL 15-9
15.2.3.2 COLDFIRE BDM COMMANDS. All ColdFire Family BDM commands include a 16-
bit operation word followed by an optional set of one or more extension words.
Operation Field
The operation field specifies the command.
R/W Field
The R/W field specifies the direction of operand transfer. When the bit is set, the transfer is
from the CPU to the development system. When the bit is cleared, data is written to the CPU
or to memory from the development system.
Table 15-3. BDM Command Summary
COMMAND MNEMONIC DESCRIPTION CPU IMPACT
1
Read A/D Register RAREG/RDREG
Read the selected address or data register and return the result
via the serial BDM interface
Halted
Write A/D Register WAREG/WDREG
The data operand is written to the specified address or data
register via the serial BDM interface
Halted
Read Memory Location READ
Read the sized data at the memory location specified by the
longword address
Cycle
Steal
Write Memory Location WRITE
Write the operand data to the memory location specified by the
longword address
Cycle
Steal
Dump Memory Block DUMP
Used in conjunction with the READ command to dump large
blocks of memory. An initial READ is executed to set up the
starting address of the block and to retrieve the first result.
Subsequent operands are retrieved with the DUMP command.
Cycle
Steal
Fill Memory Block FILL
Used in conjunction with the WRITE command to fill large
blocks of memory. An initial WRITE is executed to set up the
starting address of the block and to supply the first operand.
Subsequent operands are written with the FILL command.
Cycle
Steal
Resume Execution GO
The pipeline is flushed and refilled before resuming instruction
execution at the current PC
Halted
No Operation NOP
NOP performs no operation and may be used as a null
command
Parallel
Read Control Register RCREG Read the system control register Halted
Write Control Register WCREG Write the operand data to the system control register Halted
Read Debug Module Register RDMREG Read the Debug module register Parallel
Write Debug
Module Register
WDMREG Write the operand data to the Debug module register Halted
NOTE:
1. General command effect and/or requirements on CPU operation:
Halted - The CPU must be halted to perform this command
Steal - Command generates a bus cycle which is interleaved with CPU accesses
Parallel - Command is executed in parallel with CPU activity
Refer to command summaries for detailed operation descriptions.
15 1098765432 0
OPERATION 0 R/W
OP SIZE 0 0 A/D REGISTER
EXTENSION WORD(S)
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...