Datasheet

Debug Support
MOTOROLA MCF5206e USER’S MANUAL 15-11
The “not ready” response is ignored unless a memory bus cycle
is in progress. Otherwise, the debug module can accept a new
serial transfer after eight system clock periods.
In the third cycle, the development system supplies the low-order 16 bits of a memory
address. The debug module always returns the “not ready” response in this cycle. At the
completion of the third cycle, the debug module initiates a memory read operation. Any
serial transfers that begin while the memory access is in progress return the “not ready”
response.
Results are returned in the two serial transfer cycles following the completion of memory
access. The data transmitted to the debug module during the final transfer is the opcode for
the following command. Should a memory access generate a bus error, an error status
($10001) is returned in place of the result data.
Figure 15-5. Command Sequence Diagram
15.2.3.4 Command Set Descriptions. The BDM command set is summarized in Table 15-
3.
COMMANDS TRANSMITTED TO THE DEBUG MODULE
COMMAND CODE TRANSMITTED DURING THIS CYCLE
HIGH-ORDER 16 BITS OF MEMORY ADDRESS
LOW-ORDER 16 BITS OF MEMORY ADDRESS
SEQUENCE TAKEN IF
OPERATION HAS NOT
COMPLETED
DATA UNUSED FROM
THIS TRANSFER
SEQUENCE TAKEN IF
ILLEGAL COMMAND
IS RECEIVED BY DEBUG MODULE
RESULTS FROM PREVIOUS COMMAND
RESPONSES FROM THE DEBUG MODULE
NONSERIAL-RELATED ACTIVITY
MS ADDR
"NOT READY"
XXX
"ILLEGAL"
LS ADDR
"NOT READY"
NEXT CMD
"NOT READY"
READ (LONG)
???
NEXT CMD
"NOT READY
"
XXX
"NOT READY"
XXXXX
XXX
BERR
MS RESULT
NEXT CMD
LS RESULT
READ
MEMORY
LOCATION
NEXT
COMMAND
CODE
SEQUENCE TAKEN IF BUS
ERROR OCCURS ON
MEMORY ACCESS
HIGH- AND LOW-ORDER
16 BITS OF RESULT
XXX
REGISTER
CONTROL
REGISTER
MEMORY
LOCATION
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eescale S
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or
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