Datasheet

Debug Support
15-12 MCF5206e USER’S MANUAL MOTOROLA
Note
All the accompanying valid BDM results are defined with the
most significant bit of the 17-bit response (S/C) as 0. Invalid
command responses (Not Ready; TEA-terminated bus cycle; Il-
legal Command) return a 1 in the most significant bit of the 17-
bit response (S/C).
Motorola reserves unassigned command opcodes for future expansion. All unused com-
mand formats within any revision level will perform a NOP and return the ILLEGAL com-
mand response.
15.2.3.4.1 Read A/D Register (RAREG/RDREG). Read the selected address or data
register and return the 32-bit result. A bus error response is returned if the CPU core is not
halted.
Formats:
Command Sequence:
Operand Data:
None
Result Data:
The contents of the selected register are returned as a longword value. The data is returned
most significant word first.
15.2.3.4.2 Write A/D Register (WAREG/WDREG). The operand (longword) data is written
to the specified address or data register. All 32 register bits are altered by the write. A bus
error response is returned if the CPU core is not halted.
1514131211109876543210
$2 $1 $8 A/D REGISTER
RAREG/RDREG Command
1514131211109876543210
DATA [31:16]
DATA [15:0]
RAREG/RDREG Result
XXX
MS RESULT
NEXT CMD
LS RESULT
RAREG/RDREG
???
XXX
BERR
NEXT CMD
"NOT READY"
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