Datasheet

Debug Support
MOTOROLA MCF5206e USER’S MANUAL 15-23
of the longword are undefined. As an example, a read of the 16-bit SR returns the SR in the
lower word and undefined data in the upper word.
15.2.3.4.10 Write Control Register (WCREG). The operand (longword) data is written to
the specified control register. The write alters all 32 register bits.
Formats:
Command Sequence:
See Table 15-6 for Rc encodings.
Operand Data:
Two operands are required for this instruction. The first long operand selects the register to
which the operand data is to be written. The second operand is the data.
Result Data:
Successful write operations return a status of $0FFFF. Bus errors on the write cycle are in-
dicated by the assertion of bit 16 in the status message and by a data pattern of $0001.
15.2.3.4.11 Read Debug Module Register (RDMREG). Read the selected Debug Module
Register and return the 32-bit result. The only valid register selection for the RDMREG
command is the CSR (DRc = $0).
1514131211109876543210
$2 $8 $8 $0
$0 $0 $0 $0
$0 Rc
DATA [31:16]
DATA [15:0]
WCREG Command
EXT WORD
"NOT READY"
EXT WORD
"NOT READY"
WCREG
???
NEXT CMD
"NOT READY"
XXX
"NOT READY"
XXX
XXX
BERR
"CMD COMPLETE"
NEXT CMD
WRITE
MEMORY
LOCATION
MS DATA
"NOT READY"
LS DATA
"NOT READY"
CONTROL
REGISTER
MS ADDR
MS ADDR
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