Datasheet

Debug Support
15-26 MCF5206e USER’S MANUAL MOTOROLA
15.3 REAL-TIME DEBUG SUPPORT
ColdFire processors provide support for the debug of real-time applications. For these types
of embedded systems, the processor cannot be halted during debug but must continue to
operate. The foundation of this area of debug support is that while the processor cannot be
halted to allow debugging, the system can tolerate small intrusions into the real-time
operation.
As discussed in the previous subsection, the debug module provides a number of hardware
resources to support various hardware breakpoint functions. Specifically, three types of
breakpoints are supported: PC with mask, operand address range, and data with mask.
These three basic breakpoints can be configured into one- or two-level triggers with the
exact trigger response also programmable.
15.3.1 Theory of Operation
The breakpoint hardware can be configured to respond to triggers in several ways. The
desired response is programmed into the Trigger Definition Register. In all situations where
a breakpoint triggers, an indication is provided on the DDATA output port, when not displaying
captured operands or branch addresses, as shown in Table 15-8.
The breakpoint status is also posted in the CSR.
The BDM instructions load and configure the desired breakpoints using the appropriate
registers. As the system operates, a breakpoint trigger generates a response as defined in
the
TDR. If the system can tolerate the processor being halted, a BDM-entry can be used.
With the TRC bits of the TDR equal to $1, the breakpoint trigger causes the core to halt as
reflected in the
PST = $F status. For PC breakpoints, the halt occurs before the targeted
instruction is executed. For address and data breakpoints, the processor may have
executed several additional instructions. As a result, trigger reporting is considered
imprecise.
If the processor core cannot be halted, the special debug interrupt can be used. With this
configuration, TRC bits of the TDR equal to $2, the breakpoint trigger is converted into a
debug interrupt to the processor. This interrupt is treated higher than the nonmaskable level
7 interrupt request. As with all interrupts, it is made pending until the processor reaches a
sample point, which occurs once per instruction. Again, the hardware forces the PC
breakpoint to occur immediately (before the execution of the targeted instruction). This is
possible because the PC breakpoint comparison is enabled at the same time the interrupt
Table 15-8. DDATA[3:0], CSR[31:28] Breakpoint Response
DDATA[3:0], CSR[31:28] BREAKPOINT STATUS
$000x No Breakpoints Enabled
$001x Waiting for Level 1 Breakpoint
$010x Level 1 Breakpoint Triggered
$101x Waiting for Level 2 Breakpoint
$110x Level 2 Breakpoint Triggered
All other encodings are reserved for future use.
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