Datasheet

Debug Support
MOTOROLA MCF5206e USER’S MANUAL 15-27
sampling occurs. For the address and data breakpoints, the reporting is considered
imprecise because several additional instructions may be executed after the triggering
address or data is seen.
Once the debug interrupt is recognized, the processor aborts execution and initiates
exception processing. At the initiation of the exception processing, the core enters emulator
mode. After the standard 8-byte exception stack is created, the processor fetches a unique
exception vector, 12, from the vector table (Refer to the ColdFire Programmer’s Reference
Manual Rev 1.0 MCF5200PRM/AD).
Execution continues at the instruction address contained in this exception vector. All
interrupts are ignored while in emulator mode. You can program the debug-interrupt handler
to perform the necessary context saves using the supervisor instruction set. As an example,
this handler may save the state of all the program-visible registers as well as the current
context into a reserved memory area.
Once the required operations are completed, the return-from-exception (RTE) instruction is
executed and the processor exits emulator mode. Once the debug interrupt handler has
completed its execution, the external development system can then access the reserved
memory locations using the BDM commands to read memory.
If a hardware breakpoint (e.g., a PC trigger) is left unmodified by the debug interrupt service
routine, another debug interrupt is generated after the RTE instruction completes execution.
15.3.1.1 EMULATOR MODE. Emulator mode is used to facilitate non-intrusive emulator
functionality. This mode can be entered in three different ways:
• The EMU bit in the CSR may be programmed to force the ColdFire processor to begin
execution in emulator mode. This bit is only examined when RSTI is negated and the
processor begins reset exception processing. It may be set while the processor is
halted before the reset exception processing begins. Refer to Section 15.2.1 CPU Halt.
• A debug interrupt always enters emulation mode when the debug interrupt exception
processing begins.
• The TCR bit in the CSR may be programmed to force the processor into emulation mode
when trace exception processing begins.
During emulation mode, the ColdFire processor exhibits the following properties:
• All interrupts are ignored, including level seven.
• If the MAP bit of the CSR is set, all memory accesses are forced into a specially mapped
address space signalled by TT = $2, TM = $5 or $6. This includes the stack frame writes
and the vector fetch for the exception which forced entry into this mode.
• If the MAP bit in the CSR is set, all caching of memory accesses is disabled. Additionally,
the SRAM module is disabled while in this mode.
The return-from-exception (RTE) instruction exits emulation mode. The processor status
output port provides a unique encoding for emulator mode entry ($D) and exit ($7).
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