Datasheet

Debug Support
15-28 MCF5206e USER’S MANUAL MOTOROLA
15.3.1.2 DEBUG MODULE HARDWARE.
15.3.1.2.1 Reuse of Debug Module Hardware. The Debug Module implementation
provides a common hardware structure for both BDM and breakpoint functionality. Several
structures are used for both BDM and breakpoint purposes. Table 15-9 identifies the shared
hardware structures.
The shared use of these hardware structures means the loading of the register to perform
any specified function is destructive to the shared function. For example, if an operand
address breakpoint is loaded into the Debug Module, a BDM command to access memory
overwrites the breakpoint. If a data breakpoint is configured, a BDM write command
overwrites the breakpoint contents.
15.3.2 Concurrent BDM and Processor Operation
The debug module supports concurrent operation of both the processor and most BDM
commands. BDM commands can be executed while the processor is running, except for the
operations that access processor/memory registers:
• Read/Write Address and Data Registers
• Read/Write Control Registers
For BDM commands that access memory, the debug module requests the ColdFire core’s
bus. The processor responds by stalling the instruction fetch pipeline and then waiting until
all current core bus activity is complete. At that time, the processor relinquishes the core bus
to allow the debug module to perform the required operation. After the conclusion of the
Debug module core bus cycle, the processor reclaims ownership of the core bus.
The development system must be careful when configuring the Breakpoint Registers if the
processor is executing. The debug module does not contain any hardware interlocks;
therefore Motorola recommends that the TDR be disabled while the Breakpoint Registers
are being loaded. At the conclusion of this process, the TDR can be written to define the
exact trigger. This approach guarantees that no spurious breakpoint triggers occur.
Because there are no hardware interlocks in the debug unit, no BDM operations are allowed
while the CPU is writing the Debug Registers (SDSCLK must be inactive).
Table 15-9. Shared BDM/Breakpoint Hardware
REGISTER BDM FUNCTION BREAKPOINT FUNCTION
AATR
Bus Attributes for All Memory
Commands
Attributes for Address
Breakpoint
ABHR
Address for All Memory Commands Address for Address
Breakpoint
DBR
Data for All BDM Write Commands Data for Data Breakpoint
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