Datasheet

Debug Support
MOTOROLA MCF5206e USER’S MANUAL 15-29
NOTE
When a BDM command is serially shifted into a ColdFire micro-
processor, the debug module requests the use of the internal
bus to perform the required operation. Under certain conditions,
the processor may never grant the internal bus to the debug
module causing the BDM command to never be performed.
Specifically, the internal bus grant may be witheld from the de-
bug module if the processor is executing a tight loop where the
entire loop is contained within one aligned longword. Examples
include:
align4
label1:nop
bra.blabel1
OR
align4
label2:bra.wlabel2
The workaround is to force the loop to be aligned ACROSS two
longwords. Given this alignment, the processor correctly grants
the internal bus to the debug module.
15.3.3 Programming Model
In addition to the existing BDM commands that provide access to the processor’s registers
and the memory subsystem, the debug module contains a number of registers to support
the required functionality. All of these registers are treated as 32-bit quantities, regardless
of the actual number of bits in the implementation. The registers, known as the Debug
Figure 15-6. Debug Programming Model
ADDRESS
BREAKPOINT REGISTERS
PC BREAKPOINT
REGISTERS
DATA BREAKPOINT
REGISTERS
ABLR
ABHR
PBR
PBMR
DBMR
DBR
TDR
15
0
31
TRIGGER DEFINITION
REGISTER
ADDRESS ATTRIBUTE
TRIGGER REGISTER
AATR
7
0
15
CSR
CONFIGURATION/STATUS
REGISTER
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eescale S
emiconduct
or
, I
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