Datasheet

Debug Support
15-32 MCF5206e USER’S MANUAL MOTOROLA
The encoding for acknowledge/CPU space transfers (TT = 11) is:
000 = CPU Space Access
001 = Interrupt Acknowledge Level 1
010 = Interrupt Acknowledge Level 2
011 = Interrupt Acknowledge Level 3
100 = Interrupt Acknowledge Level 4
101 = Interrupt Acknowledge Level 5
110 = Interrupt Acknowledge Level 6
111 = Interrupt Acknowledge Level 7
15.3.3.3 PROGRAM COUNTER BREAKPOINT REGISTER (PBR, PBMR). The PC
Breakpoint Registers define a region in the instruction address space of the processor that
can be used as part of the trigger. The PBR value is masked by the PBMR value, allowing
only those bits in PBR that have a corresponding zero in PBMR to be compared with the
processor’s program counter register as defined in the TDR.
15.3.3.4 DATA BREAKPOINT REGISTER (DBR, DBMR). The Data Breakpoint Registers
define a specific data pattern that can be used as part of the trigger into debug mode.The
DBR value is masked by the DBMR value, allowing only those bits in DBR that have a
corresponding zero in DBMR to be compared with the ColdFire CPU core data signals, as
defined in the TDR.
BITS 31 0
FIELD ADDRESS
RESET -
R/W W
Program Counter Breakpoint Register (PBR)
BITS 31 0
FIELD MASK
RESET -
R/W W
Program Counter Breakpoint Mask Register (PBMR)
BITS 31 0
FIELD ADDRESS
RESET
R/W W
Data Breakpoint Register (DBR)
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...