Datasheet

Debug Support
MOTOROLA MCF5206e USER’S MANUAL 15-33
The data breakpoint register supports both aligned and misaligned operand references. The
relationship between the processor core address, the access size, and the corresponding
location within the 32-bit core data bus is shown in Table 15-12.
15.3.3.5 TRIGGER DEFINITION REGISTER (TDR). The TDR configures the operation of
the hardware breakpoint logic within the Debug module and controls the actions taken under
the defined conditions. The breakpoint logic can be configured as a one- or two-level trigger,
where bits [29:16] of the TDR define the 2nd level trigger, bits [13:0] define the first level
trigger, and bits [31:30] define the trigger response.
Reset clears the TDR.
TRC–Trigger Response Control
The trigger response control determines how the processor is to respond to a completed
BITS 31 0
FIELD MASK
RESET -
R/W W
Data Breakpoint Mask Register (DBMR)
Table 15-10. Access Size and Operand Location
CORE
ADDRESS[1:0]
ACCESS
SIZE
OPERAND
LOCATION
00 Byte Data[31:24]
01 Byte Data[23:16]
10 Byte Data[15:8]
11 Byte Data[7:0]
0x Word Data[31:16]
1x Word Data[15:0]
-x Long Data[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRC EBL EDLW EDWL EDWU EDLL EDLM EDUM EDUU DI EAI EAR EAL EPC PCI
1514131211109876543210
00 EBL EDLW EDWL EDWU EDLL EDLM EDUM EDUU DI EAI EAR EAL EPC PCI
TDR Bit Definitions
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