Datasheet

Debug Support
MOTOROLA MCF5206e USER’S MANUAL 15-35
EAR–Enable Address Breakpoint Range
If set, this bit enables the address breakpoint based on the inclusive range defined by ABLR
and ABHR.
EAL–Enable Address Breakpoint Low
If set, this bit enables the address breakpoint based on the address contained in the ABLR.
EPC–Enable PC Breakpoint
If set, this bit enables the PC breakpoint. Clearing this bit disables the PC breakpoint.
PCI–PC Breakpoint Invert
If set, this bit allows execution outside a given region as defined by PBR and PBMR to en-
able a trigger. If cleared, the PC breakpoint is defined within the region defined by PBR and
PBMR.
15.3.3.6 CONFIGURATION/STATUS REGISTER (CSR). The Configuration/Status
Register defines the operating configuration for the processor and memory subsystem. In
addition to defining the microprocessor configuration, this register also contains status
information from the breakpoint logic. The CSR is cleared during system reset. The CSR can
be read and written by the external development system and written by the supervisor
programming model.
Status–Breakpoint Status
This 4-bit field defines provides read-only status information concerning the hardware
breakpoints. This field is defined as follows:
$0 = no breakpoints enabled
$1 = waiting for level 1 breakpoint
$2 = level 1 breakpoint triggered
$5 = waiting for level 2 breakpoint
$6 = level 2 breakpoint triggered
The CSR[30-28] bits are translated and output on the DDATA[3:1] signals where x is the
31 28 27 26 25 24 23 17 16
STATUS FOF TRG HALT BKPT RESERVED IPW
1514131211109876543210
MAPTRCEMU DDC UHE BTB 0NPLIPISSM0000
CSR Bit Definitions
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