Datasheet

MOTOROLA MCF5206e USER’S MANUAL 16-1
SECTION 16
IEEE 1149.1 TEST ACCESS PORT (JTAG)
The MCF5206e includes dedicated user-accessible test logic that is fully compliant with the
IEEE standard 1149.1 Standard Test Access Port and Boundary Scan Architecture. Use the
following description in conjunction with the supporting IEEE document listed above. This
section includes the description of those chip-specific items that the IEEE standard requires
as well as those items specific to the MCF5206e implementation.
The MCF5206e JTAG test architecture implementation currently supports circuit board test
strategies that are based on the IEEE standard. This architecture provides access to all of
the data and chip control pins from the board edge connector through the standard four-pin
test access port (TAP) and the active-low JTAG reset pin, TRST. The test logic itself uses a
static design and is wholly independent of the system logic, except where the JTAG is
subordinate to other complimentary test modes (see Section 15: Debug Support section
for more information). When in subordinate mode, the JTAG test logic is placed in reset and
the TAP pins can be used for other purposes in accordance with the rules and restrictions
set forth using a JTAG compliance-enable pin.
The MCF5206e JTAG implementation can:
• Perform boundary-scan operations to test circuit board electrical continuity
• Bypass the MCF5206e device by reducing the shift register path to a single cell
• Sample the MCF5206e system pins during operation and transparently shift out the
result
• Set the MCF5206e output drive pins to fixed logic values while reducing the shift
register path to a single cell
• Protect the MCF5206e system output and input pins from backdriving and random
toggling (such as during in-circuit testing) by placing all system signal pins to high-
impedance state
NOTE
The IEEE Standard 1149.1 test logic cannot be considered
completely benign to those planning not to use JTAG capability.
You must observe certain precautions to ensure that this logic
does not interfere with system or debug operation. Refer to
Section 16.6 Disabling the IEEE 1149.1 Standard Operation.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...