Datasheet

IEEE 1149.1 Test Access Port (JTAG)
16-2 MCF5206e USER’S MANUAL MOTOROLA
16.1 OVERVIEW
Figure 16-1 is a block diagram of the MCF5206e implementation of the 1149.1 IEEE
Standard. The test logic includes several test data registers, an instruction register,
instruction register control decode, and a 16-state dedicated TAP controller.
Figure 16-1. JTAG Test Logic Block Diagram
16.2 JTAG PIN DESCRIPTIONS
The MCF5206e JTAG pin is defined to be a compliance-enable input per Section 3.8 of
the IEEE Standard 1149.1a-1993 entitled “Subordination of this Standard within a Higher
Level Test Strategy.” When JTAG is a logic 0, the MCF5206e is in JTAG mode; when
JTAG is a logic 1, the MCF5206e is in Debug mode.
BYPASS
3-BIT INSTRUCTION DECODE
3-BIT INSTRUCTION REGISTER
M
U
X
TAP
CONTROLLER
TEST DATA REGISTERS
TDI
TMS
TCK
TRST
TDO
V
+
BOUNDARY SCAN REGISTER
IDCODE REGISTER
M
U
X
V
+
V+
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