Datasheet

IEEE 1149.1 Test Access Port (JTAG)
MOTOROLA MCF5206e USER’S MANUAL 16-3
When the compliance-enable is set for JTAG mode, the pin descriptions in Table 16-1
apply.
16.3 JTAG REGISTER DESCRIPTIONS
16.3.1 JTAG Instruction Shift Register
The MCF5206e IEEE 1149.1 Standard implementation uses a 3-bit instruction-shift
register without parity. This register transfers its value to a parallel hold register and
applies one of six possible instructions on the falling edge of TCK when the TAP state
machine is in the update-IR state. To load the instructions into the shift portion of the
register, place the serial data on the TDI pin prior to each rising edge of TCK. The MSB
of the instruction shift register is the bit closest to the TDI pin and the LSB is the bit closest
to the TDO pin.
Table 16-2 lists the public customer-usable instructions that are supported along with
their encoding.
The IEEE 1149.1 Standard requires the EXTEST, SAMPLE/PRELOAD, and BYPASS
instructions. IDCODE, CLAMP and HIGHZ are optional standard instructions that the
MCF5206e implementation supports and are described in the 1149.1.
16.3.1.1 EXTEST INSTRUCTION. The external test instruction (EXTEST) selects the
boundary-scan register. The EXTEST instruction forces all output pins and bidirectional
pins configured as outputs to the preloaded fixed values (with the SAMPLE/PRELOAD
instruction) and held in the boundary-scan update registers. The EXTEST instruction can
Table 16-1. JTAG Pin Descriptions
PIN DESCRIPTION
TCK A test clock input that synchronizes test logic operations
TMS A test mode select input with a default internal pullup resistor that is sampled on the rising edge of TCK to
sequence the TAP controller
TDI A serial test data input with a default internal pullup resistor that is sampled on the rising edge of TCK
TDO A three-state test data output that is actively driven only in the Shift-IR and Shift-DR controller states and only
updates on the falling edge of TCK
TRST
An active-low asynchronous reset with a default internal pullup resistor that forces the TAP controller into the
test-logic-reset state.
Table 16-2. JTAG Instructions
INSTRUCTION ABBR CLASS
IR[2:0] INSTRUCTION SUMMARY
EXTEST EXT Required 000 Select BS register while applying fixed values to output pins and
asserting functional reset
IDCODE IDC Optional 001 Selects IDCODE register for shift
SAMPLE/
PRELOAD
SMP Required 100 Selects BS register for shift, sample, and preload without disturbing
functional operation
HIGHZ HIZ Optional 101 Selects the bypass register while three-stating all output pins and asserting
functional reset
CLAMP CMP Optional 110 Selects bypass while applying fixed values to output pins and asserting
functional reset
BYPASS BYP Required 111 Selects the bypass register for data operations
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