Datasheet

IEEE 1149.1 Test Access Port (JTAG)
MOTOROLA MCF5206e USER’S MANUAL 16-5
The HIGHZ instruction goes active on the falling edge of TCK in the update-IR state
when the data held in the instruction shift register is equivalent to octal 5.
16.3.1.5 CLAMP INSTRUCTION. The CLAMP instruction selects the bypass register
and asserts functional reset while simultaneously forcing all output pins and bidirectional
pins configured as outputs to the fixed values that are preloaded and held in the
boundary-scan update registers. This instruction enhances test efficiency by reducing
the overall shift path to a single bit (the bypass register) while conducting an EXTEST
type of instruction through the boundary-scan register. The CLAMP instruction becomes
active on the falling edge of TCK in the update-IR state when the data held in the
instruction-shift register is equivalent to octal 6.
16.3.1.6 BYPASS INSTRUCTION. The BYPASS instruction selects the single-bit
bypass register, creating a single-bit shift register path from the TDI pin to the bypass
register to the TDO pin. This instruction enhances test efficiency by reducing the overall
shift path when a device other than the MCF5206e processor becomes the device under
test on a board design with multiple chips on the overall 1149.1 defined boundary-scan
chain. The bypass register has been implemented in accordance with 1149.1 so that the
shift register stage is set to logic zero on the rising edge of TCK following entry into the
capture-DR state. Therefore, the first bit to be shifted out after selecting the bypass
register is always a logic zero (to differentiate a part that supports an IDCODE register
from a part that supports only the bypass register). The BYPASS instruction goes active
on the falling edge of TCK in the update-IR state when the data held in the instruction shift
register is equivalent to octal 7.
16.3.2 IDcode Register
An IEEE 1149.1 compliant JTAG identification register has been included on the
MCF5206e. The MCF5206e JTAG instruction encoded as octal 1 provides for reading the
JTAG IDcode register. The format of this register is defined below.
Bits 31-28 Version Number
Indicates the revision number of the MCF5206e.
Bits 27-22 Design Center
Indicates the ColdFire design center.
Bits 21-12 Device Number
Indicates an MCF5206e.
VERSIONNO 010011000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0001000000001011
1514131211109876543210
ID code Register
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