Datasheet

IEEE 1149.1 Test Access Port (JTAG)
MOTOROLA MCF5206e USER’S MANUAL 16-7
Figure 16-2. JTAG TAP Controller State Machine
16.5 RESTRICTIONS
The test logic is implemented using static logic design, and TCK can be stopped in either
a high or low state without loss of data. The system logic, however, operates on a different
TEST - LOGIC - RESET
TLR
RUN - TEST - IDLE
RTI
SELECT - DR - SCAN
SeDR
CAPTURE - IR
UPDATE - IR
EXIT2 - IR
PAUSE - IR
EXIT1 - IR
SHIFT - IR
CAPTURE - DR
UPDATE - DR
EXIT2 - DR
PAUSE - DR
EXIT1 - DR
SHIFT - DR
0
0
0
1
0
1
1
0
0
0
1
0
1
1
0
1
1
1
11
0
0
0
0
11
1 1
00
0
1
CaDR
ShDR
E1DR
PaDR
E2DR
UpDR
CaIR
ShIR
E1IR
PaIR
E2IR
UpIR
<-- VALUE OF TMS AT RISING EDGE OF TCK
SELECT - IR - SCAN
SeIR
1
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