Datasheet

IEEE 1149.1 Test Access Port (JTAG)
16-8 MCF5206e USER’S MANUAL MOTOROLA
system clock which is not synchronized to TCK internally. Any mixed operation requiring
the use of 1149.1 test logic in conjunction with system functional logic that uses both
clocks must have coordination and synchronization of these clocks done externally to the
MCF5206e.
16.6 DISABLING THE IEEE 1149.1 STANDARD OPERATION
There are two methods by which the MCF5206e can be used without the IEEE 1149.1 test
logic being active: 1) Nonuse of the JTAG test logic by either nontermination
(disconnection) or intentional fixing of TAP logic values, and 2) Intentional disabling of the
JTAG test logic by assertion of the JTAG signal (entering Debug mode).
There are several considerations that must be addressed if the IEEE 1149.1 logic is not
going to be used once the MCF5206e is assembled onto a board. The prime
consideration is to ensure that the IEEE 1149.1 test logic remains transparent and benign
to the system logic during functional operation. This requires the minimum of either
connecting the TRST pin to logic 0, or connecting the TCK clock pin to a clock source that
will supply five rising edges and the falling edge after the fifth rising edge, to ensure that
the part enters the test-logic-reset state. The recommended solution is to connect TRST
to logic 0. Another consideration is that the TCK pin does not have an internal pullup as
is required on the TMS, TDI, and TRST pins; therefore, it should not be left unterminated
to preclude mid-level input values. Figure 16-3 shows pin values recommended for
disabling JTAG with the MCF5206e in JTAG mode (JTAG=0).
Figure 16-3. Disabling JTAG in JTAG Mode
A second method of using the MCF5206e without the IEEE 1149.1 logic being active is to
select debug mode by placing a logic 1 on the defined compliance enable pin, JTAG.
When JTAG is a logic 1, then the IEEE 1149.1 test controller is placed in the test-logic-
reset state by the internal assertion of the TRST signal to the controller, and, the TAP pins
function as Debug mode pins. While in JTAG mode, input pins TDI/DSI, TMS/BKPT
, and
JTAG
TDI/DSI
TCK
V
DD
TRST/DSCLK
TMS/BKPT
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Freescale Semiconductor, Inc.
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