Datasheet

Introduction
MOTOROLA MCF5206e USER’S MANUAL 1-13
Table 1-4. Instruction Set Summary
INSTRUCTION OPERAND SYNTAX OPERAND SIZE OPERATION
ADD Dy,<ea>x
<ea>y,Dx
32
32
Source + Destination → Destination
ADDA <ea>y,Ax 32 Source + Destination → Destination
ADDI #<data>,Dx 32 Immediate Data + Destination → Destination
ADDQ #<data>,<ea>x 32 Immediate Data + Destination → Destination
ADDX Dy,Dx 32 Source + Destination + X → Destination
AND Dy,<ea>x
<ea>y,Dx
32
32
Source & Destination → Destination
ANDI #<data>,Dx 32 Immediate Data & Destination → Destination
ASL Dy,Dx
#<data>,Dx
32
32
X/C ← (Dx << Dy) ← 0
X/C ← (Dx << #<data>) ← 0
ASR Dy,Dx
<data>,Dx
32
32
MSB → (Dx >> Dy) → X/C
MSB → (Dx >> #<data>) → X/C
Bcc <label> 8,16 If Condition True, Then PC + 2 + d
n
→ PC
BCHG Dy,<ea>x
#<data>,<ea>x
8,32
8,32
~(<Bit Number> of Destination) → Z,
Bit of Destination
BCLR Dy,<ea>x
#<data>,<ea>x
8,32
8,32
~(<Bit Number> of Destination) → Z;
0 → Bit of Destination
BRA <label> 8,16 PC + 2 + d
n
→ PC
BSET Dy,<ea>x
#<data>,<ea>x
8,32
8,32
~(<Bit Number> of Destination) → Z;
1→ Bit of Destination
BSR <label> 8,16 SP – 4 → SP; next sequential PC→ (SP); PC + 2 + d
n
→ PC
BTST Dy,<ea>x
#<data>,<ea>x
8,32
8,32
~(<Bit Number> of Destination) → Z
CLR <ea>x 8,16,32 0 → Destination
CMPI #<data>,Dx 32 Destination – Immediate Data
CMP <ea>y,Dx 32 Destination – Source
CMPA <ea>y,Ax 32 Destination – Source
CPUSHL (Ax) none Push and Invalidate Cache Line
DIVS <ea>y,Dx 16
32
Dx /<ea>y → Dx {16-bit Remainder; 16-bit Quotient}
Dx /<ea>y → Dx {32-bit Quotient}
Signed operation
DIVU <ea>y,Dx 16 Dx /<ea>y → Dx {16-bit Remainder; 16-bit Quotient}
Dx /<ea>y → Dx {32-bit Quotient}
Unsigned operation
EOR Dy,<ea>x 32 Source ^ Destination → Destination
EORI #<data>,Dx 32 Immediate Data ^ Destination → Destination
EXT Dx
Dx
8 → 16
16 → 32
Sign-Extended Destination → Destination
EXTB Dx 8 → 32 Sign-Extended Destination → Destination
HALT none none Enter Halted State
JMP <ea> none Address of <ea> → PC
JSR <ea> 32 SP – 4 → SP; next sequential PC → (SP); <ea> → PC
LEA <ea>y,Ax 32 <ea> → Ax
LINK Ax,#<data> 16 SP – 4 → SP; Ax → (SP); SP → Ax; SP + d16 → SP
LSL Dy,Dx
#<data>,Dx
32
32
X/C ← (Dx << Dy) ← 0
X/C ← (Dx << #<data>) ← 0
LSR Dy,Dx
#<data>,Dx
32
32
0 → (Dx >> Dy) → X/C
0 → (Dx >> #<data>) → X/C
MAC Ry,Rx <shift>
Ry,Rx<shift>,<ea>y,Rw
16 × 16 + 32 → 32
32 → 32
ACC + (Ry × Rx){<< 1 | >> 1} → ACC
ACC + (Ry × Rx){<< 1 | >> 1} → ACC; (<ea>y{&MASK}) → Rw
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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